A semiconductor chip with a circuit element formed thereon is packaged on a package substrate for electric connection between chips. At that time, it is necessary that an electrode of a semiconductor chip be electrically connected to an electrode formed on a package substrate. As a method for this purpose, the flip chip technique as shown in FIGS. 1a and 1b generally used. In this technique, a solder ball 3 is formed on the external output terminal of a chip 1, separately, a solder bump 12 is formed on wiring 11 of a package substrate 10 and both of them are connected by reflow. Here, the solder ball 3 on the semiconductor chip 1 is made of a solder of a higher melting point than that of a solder related to the solder bump 12 and does not fuse by reflow. For example, the solder bump 12 is made of eutectic solder (63 wt. % tin/37 wt. % lead), whereas the solder ball 3 made of solder (97 wt. % tin/3 wt. % lead) having a higher melting point. In addition, wiring 11 on the package substrate 10 does not fuse even after reflow because of being generally made of gold or copper. A multi-layered printed board, such as an SLC (Surface Laminated Circuitry) substrate formed by the buildup process, is often used as the package substrate 10.
The flip-chip technique requires that a solder 12 be used to form a connection to the package substrate. This connection is needed because the space H between the semiconductor chip 1 and the package substrate 10 needs to be maintained.
The space H is a parameter for the connection life of a product. That is, the connection life Nf is given by Nf=M.cndot.H/(.DELTA..alpha..cndot.l.cndot..DELTA.T), where M is the connection constant dependent on a connection material; .DELTA..alpha. is the difference in thermal expansion factor between a semiconductor chip and a package substrate; l is the distance from the center of a semiconductor chip to a bump at the outermost circumference; and .DELTA.T is the temperature range in a heat cycle. When all of the factors except H are balanced, the connection life depends upon the space H between the semiconductor chip and the package substrate after connection. Thus, forming solder bumps 12 for connection on the semiconductor substrate is needed to increase the value of H.
However, forming solder bumps for connection on the surface of the semiconductor substrate is problematic. There is a need for forming a solder ball 3 on the surface of the chip and a solder bump 12 on the surface of the package substrate, but supplying solder at a plurality of spots to achieve a single electric connection in this manner complicates the process and accordingly presents a problem from the standpoint of productivity. In addition, forming such a solder bump 12 obstructs the pitch of a pad to be miniaturized, thereby making it difficult to implement a higher-density package substrate. Furthermore, a solder bump is generally formed by the screen printing process, but a mask used in this process is expensive and a change in the specification thereof is difficult.
A relevant technique,is disclosed in Published Unexamined Patent Application No. 3-62926. In that application, a solder bump is structured by forming a high-melting-point solder layer on an electrode which is formed on the substrate, with a low-melting-point solder layer thereon. The high-melting-point solder layer never fuses in soldering, therefore this structure has an advantage in that a definite space H can be maintained. However, since the thickness of the superficial low-melting-point solder layer is small, a high-melting-point solder layer has to be formed thickly, which is difficult in view of process. In addition, according to the structure disclosed, the shape of a mushroom having a wide cap requires a large pitch between the solder bumps, which clearly hinders a high-density packaging.
Also, Published Unexamined Patent Application No. 5-243233 discloses a bump structured by forming a lower layer of copper and coating the portion exposed above the insulating layer with an upper layer made of gold. However, the gold coating in this invention is applied to provide stability for the copper underlayer, but does not aim at prolonging the connection life and promoting the productivity of forming the solder bump in a flip chip connection.
It is one objective of the present invention to perform soldering by forming a solder layer only on the surface of a semiconductor chip without forming a solder bump on the surface of a package substrate while keeping the space H between the package substrate and the semiconductor chip greater than a predetermined value.
It is another object of the present invention to provide the structure of a solder bump for connection which does not hinder the high integration of a package substrate while achieving the above task. For this purpose, a structure in which a cap portion of the upper layer spreads out sideways only at the minimum and a producing method thereof are given.